1. Field of the Invention
The present invention relates to semiconductor fabrication, in particular, to solder bumps on a semiconductor substrate and fabrication methods thereof.
2. Brief Discussion of Related Art
The reduction of the feature sizes of semiconductor devices using advanced semiconductor techniques, such as high-resolution lithography and directional etching, have dramatically increased the device packing density on integrated circuit chips formed on a substrate. However, as device packing density increases, the number of electrical metal interconnect layers on the chip must be increased to effectively wire up the discrete devices on the substrate while reducing the chip size. Typically after completing the multilevel interconnect structure, aluminum bonding pads are formed on the top surface of the interconnect structure to provide external electrical connections to the chip. A passivation layer is then applied to passivate the chip from moisture and contamination.
US patent publication no. 20040182915 to Bachman et al. discloses a method comprising forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.
U.S. Pat. No. 6,617,674 to Becker et al. discloses a semiconductor package comprising a wafer having an active surface comprising at least one integrated circuit, wherein each integrated circuit has a plurality of bond pads; a cured silicone layer covering the surface of the wafer, provided that at least a portion of each bond pad is not covered with the silicone layer and wherein the silicone layer is prepared by the method of the invention. There are, however, still some problems regarding bond pad oxidation and stress.
Therefore, there is still a need to provide a solder bump on a semiconductor substrate and fabrication method thereof to further prevent the copper bond pad from oxidation during a thermal ambient.
Furthermore, there is still a need to provide a solder bump on a semiconductor substrate and fabrication method thereof to reduce the stresses created by the package of the integrated circuit chip.